RISC-V /Debug /Machine Context (32-bit mcontext)

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Interpret as Machine Context (32-bit mcontext)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0hcontext

Description

This register must be implemented if {csr-hcontext} is implemented, and is optional otherwise. It is only accessible in M-mode and Debug mode.

đź“Ś NOTE

{mcontext-hcontext} is primarily useful to set triggers on hypervisor systems that only fire when a given VM is executing. It is also useful in systems where M-Mode implements something like a hypervisor directly.

Fields

hcontext

M-Mode or HS-Mode (using {csr-hcontext}) software can write a context number to this register, which can be used to set triggers that only fire in that specific context.

An implementation may tie any number of upper bits in this field to 0. If the H extension is not implemented, it’s recommended to implement 6 bits on RV32 and 13 bits on RV64 (as visible through the {csr-mcontext} register). If the H extension is implemented, it’s recommended to implement 7 bits on RV32 and 14 bits on RV64.

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